Semiconductor memory device

ABSTRACT

A first interlayer insulating film having a second contact hole is formed on a main surface of a semiconductor substrate 1 in a peripheral circuitry. A second plug electrode of the same material as a first plug electrode in a memory cell array is formed in the second contact hole. A pad layer is formed over the second plug electrode and a top surface of the first interlayer insulating film. The pad layer and a capacitor lower electrode are made of the same material. The pad layer is covered with the second interlayer insulating film. A third contact hole is formed at a portion of the second interlayer insulating film located above the pad layer. A first aluminum interconnection layer is formed in the third contact hole. Thereby, a contact can be formed easily between the interconnection layer and the main surface of the semiconductor substrate in the peripheral circuitry of a DRAM, and a manufacturing process can be simplified.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor memory device and amethod of manufacturing the same, and in particular to a structure of aDRAM (dynamic random access memory) and a method of manufacturing thesame.

2. Description of the Related Art

A demand for semiconductor memory devices is rapidly increasing owing towide use of information equipment such as computers. From a functionalstandpoint, devices having a large scale storage capacity and capable ofoperating at a high speed are in great demand. Correspondingly,technology has been developed for improving the degree of integration,speed and reliability of the semiconductor memory device.

DRAMs (Dynamic Random Access Memories) are well known as semiconductormemory devices which allow random input and output of storageinformation. In general, the DRAM is formed of a memory cell array whichis a storage region storing a large number of storage information and aperipheral circuitry for controlling an operation of the memory cellarray.

FIG. 28 is a block diagram showing structures of a conventional DRAM.Referring to FIG. 28, a DRAM 150 includes memory cell array 151 forstoring data signals of storage information, row and column addressbuffer 152 for externally receiving an address signal which is used forselecting a memory cell forming a unit storage circuit, row and columndecoders 153 and 154 for decoding the address signal and therebydesignating a memory cell, sense refresh amplifier 155 for amplifyingand reading a signal stored in the designated memory cell, data-in anddata-out buffers 156 and 157 for input and output of data, and clockgenerator 158 for generating a clock signal.

The memory cell array 151 which occupies a large area on thesemiconductor chip is formed of a plurality of memory cells which arearranged in a matrix form and each are adapted to store the unit storageinformation. Each memory cell is formed of one MOS (Metal OxideSemiconductor) transistor and one capacitor connected thereto. Thememory of the above structure is called a memory cell ofone-transistor/one-capacitor type. Since the memory cell of this typehas a simple structure, degree of integration of the memory cell arraycan be easily increased. By this reason, they are widely used in DRAMsof a large capacity.

The memory cells of the DRAMs are classified into several types inaccordance with structures of capacitors. In a stacked type capacitormemory cell, a major portion of the capacitor is extended up topositions above a gate electrode and a field isolating film forincreasing an area of opposed portions of electrodes in the capacitor.

This can increase a capacitor capacitance. The stacked type capacitorhaving the above feature can ensure a sufficient capacitor capacitanceeven if elements are miniaturized in accordance with high integration ofthe semiconductor device. Consequently, the stacked type capacitors havebeen widely used in accordance with high integration of thesemiconductor memory devices.

However, it is difficult to ensure an intended capacitor capacitance inthe stacked type capacitor described above, if elements are furtherminiaturized for forming a DRAM, e.g., of 256 Mbits.

In order to increase the capacitor capacitance, it has been attempted touse a high dielectric film such as PZT (lead zirconate titanateceramics). FIGS. 29A and 29B show an example of a DRAM in which the highdielectric film such as PZT is used as the dielectric film of capacitor.

Referring to FIGS. 29A and 29B, the DRAM includes a memory cell arrayand a peripheral circuitry as described above. A structure of the memorycell array of the conventional DRAM will now be described below. In thememory cell array, a p-type semiconductor substrate 201 is provided atits main surface with an element isolating region, at which a fieldoxide film 202 is formed. Semiconductor substrate 201 is also providedat its main surface with an element forming region, at which transfergate transistors 204a and 204b are formed.

Transfer gate transistor 204a includes n-type impurity regions 203a and203b, which are formed at the main surface of semiconductor substrate201 with a space between each other for forming source/drain regions,and a gate electrode (word line) 207a formed on a channel region betweenimpurity regions 203a and 203b with a gate insulating film 206atherebetween.

Transfer gate transistor 204b includes n-type impurity regions 203b and203c forming source/drain regions, and a gate electrode 207b formed on achannel region between impurity regions 203b and 203c with a gateinsulating film 206b therebetween.

Gate electrodes 207c and 207d of another transfer gate transistor areextended over field oxide film 202. Gate electrodes 207a, 207b, 207c and207d are covered with oxide films 209. A buried bit line 210 is formedon impurity region 203b and is electrically connected thereto. Buriedbit line 210 is covered with an insulating layer 212.

Insulating layer 212 and oxide films 209 are covered with a firstinterlayer insulating film 214 having a flattened top surface. Firstinterlayer insulating film 214 is provided with first contact holes 215located above impurity regions 203a, 203c and 203d.

In contact holes 215 are formed first plug electrodes 216 electricallyconnected to impurity regions 203a, 203c and 203d, respectively.Capacitor lower electrodes 217 are formed on first plug electrodes 216with barrier layers 229 interposed therebetween and are electricallyconnected thereto. Capacitor lower electrodes 217 may be formed ofplatinum (Pt). Barrier layers 229 prevent diffusion between the materialof capacitor lower electrode 217 and the material of first plugelectrode 216.

Capacitor lower electrodes 217 are covered with a capacitor dielectricfilm 218, which is formed of high dielectric material such as SrTiO₃.Capacitor dielectric film 218 is covered with a capacitor upperelectrode 219, which is formed of material such as platinum (Pt).

Capacitor upper electrode 219 is covered with a second interlayerinsulating film 220 having a flattened top surface. A distance D betweenthe top surface of second interlayer insulating film 220 and the mainsurface of semiconductor substrate 201 is about 1.7 μm.

First aluminum interconnection layers 221 are formed on secondinterlayer insulating film 220 with a space between each other. Firstaluminum interconnection layers 221 are covered with a protective film222, on which second aluminum interconnection layer 223 is formed.Capacitor lower electrodes 217, capacitor dielectric film 218 andcapacitor upper electrode 219 form a capacitor 224.

Now, a structure of the peripheral circuitry of the conventional DRAMwill be described below. In the peripheral circuitry shown in FIG. 29B,field oxide films 202 which are spaced from each other are formed at theelement isolating regions in the main surface of p-type semiconductorsubstrate 201. AMOS transistor 205 is formed at the element formingregion in the main surface of semiconductor substrate 210.

MOS transistor 205 includes n-type impurity regions 203f and 203gforming source/drain regions, and a gate electrode 208 formed on achannel region between impurity regions 203f and 203g with a gateinsulating film 206c therebetween. An impurity region 203e of anothertransistor is formed at the element forming region in the main surfaceof semiconductor substrate 201.

A polysilicon pad 211a is formed on impurity region 203f and iselectrically connected thereto. A polysilicon pad 211b is formed onimpurity region 203g and is electrically connected thereto. Polysiliconpad 211a is covered with an insulating layer 213. Gate electrode 208 iscovered with an oxide film 209a.

A first interlayer insulating film 214a is formed over the main surfaceof semiconductor substrate 201. A second interlayer insulating film 220ais formed on first interlayer insulating film 214a. Second interlayerinsulating film 220a is formed at the peripheral circuitry when secondinterlayer insulating film 220 is formed at the memory cell array.Second interlayer insulating film 220a contributes to ensure insulationbetween first aluminum interconnection layers 221a, which will bedescribed later, and conductive layers formed on semiconductor substrate210. However, even if second interlayer insulating film 220a wereeliminated, insulation between first aluminum interconnection layer 221aand the conductive layers on semiconductor substrate 210 would beensured by first interlayer insulating film 214a.

There are formed second contact holes 215a penetrating first and secondinterlayer insulating films 214a and 220a. A depth D2 of second contactholes 215a varies depending on a position of them, and is in a rangefrom about 0.8 μm to about 2.0 μm. The depth specifically varies inaccordance with variation of film thicknesses of first and secondinterlayer insulating films 214a and 220a due to irregular or steppedshape of the bases of them.

Second plug electrodes 216a made of, e.g., polysilicon are formed insecond contact holes 215a. First aluminum interconnection layers 221aare formed on second plug electrodes 216a. First aluminuminterconnection layers 221a are covered with a protection layer 222a, onwhich second aluminum interconnection layer 223a is formed.

A method manufacturing the conventional DRAM having the above structurewill be described below. FIGS. 30A and 30B to 36A and 36B arefragmentary cross sections showing 1st to 7th steps in the process ofmanufacturing the conventional DRAM.

Referring first to FIGS. 30A and 30B, field oxide films 202 are formedat the element isolating regions on the main surface of semiconductorsubstrate 201, e.g., by a LOCOS (Local Oxidation Of Silicon) method.Then, gate insulating films 206a, 206b and 206c are formed, e.g., by athermal oxidation method. In the memory cell array, gate electrodes(word lines) 207a, 207b, 207c and 207d are selectively formed on gateinsulating films 206a and 206b as well as field oxide films 202. At thesame time, gate electrode 208 is formed on gate insulating film 206c inthe peripheral circuitry.

Then, impurity is implanted into the main surface of semiconductorsubstrate 201 using gate electrodes 207a, 207b and 208 and field oxidefilms 202 as a mask. Thereby, impurity regions 203a, 203b, 203c and 203dare formed in the memory cell array, and impurity regions 203e, 203f and203g are formed in the peripheral circuitry.

Then, oxide films 209 and 209a are formed over gate electrodes 207a,207b, 207c and 208. A polysilicon layer is formed over the whole mainsurface of semiconductor substrate 201, and then is patterned into apredetermined configuration. Thereby, buried bit line 210, which iselectrically connected to impurity region 203b, is formed on impurityregion 203b in the memory cell array. At the same time, polysilicon pad211a electrically connected to impurity region 203f is formed onimpurity region 203f in the peripheral circuitry.

Insulating layers 212 and 213 are formed to cover buried bit line 210and polysilicon pad 211a. Then, a polysilicon layer is deposited overthe whole main surface of semiconductor substrate 201. This polysiliconlayer is patterned to form polysilicon pad 211b on impurity region 203gelectrical connected thereto.

Then, a CVD method or the like is used to form first interlayerinsulating films 214 and 214a made of, e.g., BPSG (Boro-Phospho SilicateGlass) on the whole main surface of semiconductor substrate 201.Flattening processing is effected on first interlayer insulating films214 and 214a.

Referring to FIGS. 31A and 31B, first contact holes 215 reaching thesurfaces of impurity regions 203a, 203c and 203d are formed at firstinterlayer insulating film 214 in the memory cell array. A polysiliconlayer (not shown) filling first contact holes 215 is formed over firstinterlayer insulating film 214 to fill first contact holes 215. Etchbackis effected on the polysilicon layer to form first plug electrodes 216made of polysilicon in first contact holes 215.

Referring to FIGS. 32A and 32B, barrier layers 229 made of TiN andcapacitor lower electrodes 217 made of, e.g., platinum (Pt) are formedon plugs 216 by a sputtering method or the like. Capacitor dielectricfilm 218 made of high dielectric material is formed to cover capacitorlower electrode 217 by a sputtering method or the like.

Capacitor dielectric film 218 may be made of tantalum oxide (TaO₂), leadzirconate titanate (PZT), lead lanthanum zirconate titanate (PLZT),strontium titanate (STO) or barium titanate (BTO).

Capacitor upper electrode 219 made of, e.g., platinum (Pt) is formed oncapacitor dielectric film 218 by a sputtering method or the like.Thereby, capacitors 224 each including capacitor lower electrode 217,capacitor dielectric film 218 and capacitor upper electrode 219 areformed on first interlayer insulating film 214.

Referring to FIGS. 33A and 33B, second interlayer insulating film 220made of, e.g., a BPSG film is formed on capacitor upper electrode 219 inthe memory cell array by a CVD method or the like. At the same time,second interlayer insulating film 220a is formed on first interlayerinsulating film 214 in the peripheral circuitry. Flattening processingis effected on second interlayer insulating films 220 and 220a.

Referring to FIGS. 34A and 34B, second contact holes 215a penetratingfirst and second interlayer insulating films 214a and 220a are formed inthe peripheral circuitry. Depth D2 of second contact holes 215 thusformed in the peripheral circuitry varies within a large range fromabout 0.8 μm to about 2.0 μm.

Second contact holes 215a have depth D2 of various values due to thefact that film thicknesses of first and second interlayer insulatingfilms 214a and 220a varies depending on their position on semiconductorsubstrate 201 due to irregular or stepped shaped of their bases.

Referring now to FIGS. 35A and 35B, second plug electrodes 216a made of,e.g., polysilicon are formed in second contact holes 215a formed in theperipheral circuitry. Second plug electrodes 216a are required due tothe fact that second contact holes 215a have the depth of various valuesfrom about 0.8 μm to about 2.0 μm as described above.

Referring to FIGS. 36A and 36B, first aluminum interconnection layers221 which are spaced from each other are formed on second interlayerinsulating film 220 in the memory cell array by a sputtering method orthe like. At the same time, first aluminum interconnection layers 221aare formed on the top surfaces of second plug electrodes 216a in theperipheral circuitry.

Thereafter, protective films 222 and 222a are formed to cover firstaluminum interconnection layers 221 and 221a, and second aluminuminterconnection layers 223 and 223a are formed over protective films 222and 222a, respectively. Through the steps described above, theconventional DRAM shown in FIGS. 29A and 29B is completed.

The conventional DRAM described above, however, has problems which willbe described below with reference to FIGS. 37 and 38. FIG. 37 shows afirst problem of the conventional DRAM, and is a fragmentary crosssection of the peripheral circuitry at a 5th step in the process ofmanufacturing the conventional DRAM. FIG. 38 shows a third problem ofthe conventional DRAM, and is a fragmentary cross section of theperipheral circuitry at a 7th step in the process of manufacturing theconventional DRAM.

The first problem of the conventional DRAM will now be described belowwith reference to FIG. 37. As shown in FIG. 37, depth D2 of secondcontact holes 215a formed at the peripheral circuitry in theconventional DRAM varies within a range from a small value less thanabout 1 μm to large values of about 1.8 μm to about 2.0 μm. Thus, depthD2 of second contact holes 215a varies to a relatively large extent.

Meanwhile, second contact holes 215a generally have an open width W of asubstantially constant value from about 0.6 μm to about 0.8 μm.Therefore, the aspect ratio of second contact holes 215a varies within arange from a small value of about 1 to a large value from 2 to 3 ormore. Thus, the aspect ratio varies to a relatively large extent.

In accordance with higher integration, however, open width W of secondcontact holes 215a is reduced. This further increases the value ofaspect ratio of contact holes 215a. In other words, in accordance withhigher integration, the value of aspect ration further increases. As aresult, higher integration makes it extremely difficult to form secondcontact holes 215a in the peripheral circuitry.

Now, a second problem of the conventional DRAM will be described below.This problem is caused by the above increase of aspect ration of secondcontact holes 215a in accordance with higher integration.

The increase of aspect ratio of second contact holes 215a in accordancewith the integration causes the following necessity. Second contactholes 215a must be filled, e.g., with second plug electrodes 216a so asto make contact between first aluminum interconnection layers 221a andimpurity regions 203e, 203f and 203g.

More specifically, extra steps must be employed for forming second plugelectrodes 216a within second contact holes 215a so as to make contactbetween first aluminum interconnection layer 221a and impurity regions203e, 203f and 203g in the peripheral circuitry. This increases amanufacturing cost and complicates the manufacturing process.

The third problem of the conventional DRAM will be described below withreference to FIG. 38. As already described, open width W of secondcontact holes 215a in the peripheral circuitry decreases in accordancewith higher integration as shown in FIG. 38. A plan width W1 of firstaluminum interconnection layers 221a formed on second contact holes 215aalso decreases.

This reduces a maximum allowable magnitude of dislocation of the maskused for patterning first aluminum interconnection layers 221a. As aresult, the structure of conventional DRAM causes the problem thatformation of first aluminum interconnection layers 221a becomesdifficult in accordance with higher integration.

SUMMARY OF THE INVENTION

The present invention has been developed in view of the above matters.An object of the invention is to provide a semiconductor memory devicehaving a structure in which contact holes can be formed easily in aperipheral circuitry, and a method of manufacturing the same.

Another object of the invention is to provide a semiconductor memorydevice having a structure allowing reduction of a manufacturing cost,and a method of manufacturing the same.

Still another object of the invention is to provide a semiconductormemory device having a structure which facilitates formation of acontact between a first aluminum interconnection layer in a peripheralcircuitry and an impurity region at a main surface of a semiconductorsubstrate without increasing a manufacturing cost, and a method ofmanufacturing the same.

A semiconductor memory device according to the invention generallyincludes a structure in which a memory cell array (memory cell portion)including memory cells storing information and a peripheral circuitry(peripheral circuit portion) including peripheral circuits controllingan operation of the memory cells are formed on a main surface of asemiconductor substrate.

The semiconductor memory device according to the invention includes afirst interlayer insulating film which is provided with a first openingat a predetermined position on the main surface of the semiconductorsubstrate in the memory cell array and a second opening at apredetermined position on the main surface of the semiconductorsubstrate in the peripheral circuitry, first and second plug electrodesformed in the first and second openings, respectively, and areelectrically connected to the main surface of the semiconductorsubstrate, a capacitor lower electrode formed on and electricallyconnected to the first plug electrode, a capacitor dielectric filmcovering the capacitor lower electrode, a capacitor upper electrodecovering the capacitor dielectric film, a pad layer formed over a topsurface of the second plug electrode and a top surface of the firstinterlayer insulating film and electrically connected to the second plugelectrode, a second interlayer insulating film formed over the pad layerand having a third opening located above the pad layer, and aninterconnection layer formed at least in the third opening andelectrically connected to the pad layer.

The pad layer and the capacitor lower electrode are preferably made ofthe same material. The capacitor lower electrode and the first plugelectrode are preferably integral with each other, and the pad layer andthe second plug electrode are preferably integral with each other. Thepad layer and the capacitor lower electrode are preferably made of noblemetal having a high melting point.

According to the semiconductor memory device of the above aspect of theinvention, a contact which electrically connects the interconnectionlayer formed in the peripheral circuitry to the main surface of thesemiconductor substrate is formed of the third opening formed at thesecond interlayer insulating film, the interconnection layer formed inthe third opening, the pad layer, the second opening formed at the firstinterlayer insulating film, and the second plug electrode formed in thesecond opening.

The pad layer is formed on the second plug electrode. The pad layer ispreferably formed over the second plug electrode and the top surface ofthe first interlayer insulating film. This ensures a large area of thetop surface of the pad layer. The large area of the top surface of thepad layer increases a degree of freedom relating to a position of thethird opening. This facilitates formation of the third opening.

The second opening is formed at the first interlayer insulating film.The third opening is formed at the second interlayer insulating film.Thereby, the second and third openings have depths smaller than those ofopenings (contact holes) formed in the conventional peripheralcircuitry. Therefore, aspect ratios of the second and third openings canbe smaller than those of the openings formed in the conventionalperipheral circuitry.

Consequently, the second and third openings can be formed more easilythan the openings in the conventional peripheral circuitry. Owing to theabove matters, the contacts between the insulating layers and thesemiconductor substrate can be formed more easily than the prior art.

Since the degree of freedom relating to the position of the thirdopening increases, the third opening can be formed at a position shiftedfrom a position of the second opening. Thereby, a large region can beensured for forming the interconnection layers even if the degree ofintegration increases. As a result, the interconnection layers can beformed relatively easily even if the degree of integration increases.

If the pad layer and capacitor lower electrode are made of the samematerial, the pad layer and capacitor lower electrode can be formed atthe same step(s). This simplifies the manufacturing process. If thefirst plug electrode and capacitor lower electrode are formed integrallywith each other, and the second plug electrode and pad layer are formedintegrally with each other, the first plug electrode and capacitor lowerelectrode can be formed at the same step(s), and the second plugelectrode and pad layer can be formed at the same step(s). Therefore,the manufacturing process is simplified.

The pad layer may be made of platinum (Pt), in which case followingoperation and effect are obtained. The platinum forms a base of thethird opening. In connection with the step of forming the third opening,the platinum has a good resistance against over-etching. Therefore, thethird opening can be formed easily. The platinum is stable material andhence is resistive to oxidation. Therefore, good contact can be madebetween the interconnection layer and pad layer.

According to a method of manufacturing a semiconductor memory device ofan aspect of the invention, a first interlayer insulating film is formedto cover a memory cell portion and a peripheral circuit portion, a firstopening is formed to expose a part of the memory cell portion, and asecond opening is formed to expose a part of the peripheral circuitportion. First and second plug electrodes which are electricallyconnected to a part of the memory cell portion and a part of theperipheral circuit portion in the first and second openings,respectively. A conductive layer is formed to cover top surfaces of thefirst and second plug electrodes and a top surface of the firstinterlayer insulating film. The conductive layer is patterned to form acapacitor lower electrode on the top surface of the first plugelectrode, and a pad layer is formed on the top surface of the secondplug electrode. A capacitor dielectric film and a capacitor upperelectrode are sequentially formed to cover the capacitor lowerelectrode. A second interlayer insulating film is formed to cover thepad layer and the capacitor upper electrode. A third opening locatedabove the pad layer is formed at the second interlayer insulating film.An interconnection layer electrically connected to the pad layer isformed at least in the third opening.

According to the method of manufacturing the semiconductor memory deviceof the above aspect of the invention, the second plug electrode of theperipheral circuitry is formed at the same step as that of forming thefirst plug electrode for connecting the capacitor lower electrode to thesemiconductor substrate in the memory cell array (memory cell portion).The pad layer in the peripheral circuitry (peripheral circuit portion)is formed at the same step as that of forming the capacitor lowerelectrode in the memory cell array. Therefore, the second plug electrodeand pad layer are formed in the peripheral circuitry without requiringany additional step.

The third opening covering the pad layer is formed at the secondinterlayer insulating film. Therefore, the third opening is shallowerthan an opening formed in the conventional peripheral circuitry. Thethird opening is required only to be located on the pad layer, so thatthe top surface of the pad layer can have a large area, whereby thedegree of freedom relating to a position of the third opening can berelatively large. Thereby, the third opening can be formed easily.

The interconnection layer is formed in the third opening. In thismanner, the contact is formed to make electrical connection between theinterconnection layer in the peripheral circuitry and the main surfaceof the semiconductor substrate, so that it is possible to eliminate astep exclusively used for forming the plug electrode making electricalconnection between the interconnection layer in the peripheral circuitryand the main surface of the semiconductor substrate. Therefore, themanufacturing process can be simpler than the prior art, and themanufacturing cost can be low.

A method of manufacturing a semiconductor memory device of anotheraspect of the invention, a first interlayer insulating film is formed tocover a memory cell portion and a peripheral circuit portion, a firstopening is formed to expose a part of the memory cell portion and asecond opening is formed to expose a part of the peripheral circuitportion. A conductive layer which fills the first and second openings isformed over a top surface of the first interlayer insulating film. Theconductive layer is patterned to form a capacitor lower electrodecovering the first opening and electrically connected to a part of thememory cell portion, and a pad layer covering the second opening andelectrically connected to a part of the peripheral circuit portion. Acapacitor dielectric film and a capacitor upper electrode aresequentially formed over the capacitor lower electrode. A secondinterlayer insulating film is formed over the pad layer and thecapacitor upper electrode. A third opening is formed at the secondinterlayer insulating film located above the pad layer. Aninterconnection layer electrically connected to the pad layer is formedat least in the third opening.

According to the method of manufacturing the semiconductor memory deviceof the above aspect, the capacitor lower electrode is partiallyconfigured to having a function as the first plug electrode, and the padlayer is partially configured to have a function as the second plugelectrode. Thus, the capacitor lower electrode and first plug electrodeare integral with each other, and the pad layer and second plugelectrode are integral with each other.

Thereby, the capacitor lower electrode and first plug electrode can beformed at the same step, and the pad layer and second plug electrode canbe formed at the same step. Therefore, the manufacturing process can befurther simplified compared with the above case.

The foregoing and other objects, features, aspects and advantages of thepresent invention will become more apparent from the following detaileddescription of the present invention when taken in conjunction with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A and 1B are fragmentary cross sections of a DRAM of a firstembodiment of the invention;

FIGS. 2A and 2B-9A and 9B are fragmentary cross sections showing 1st to8th steps in a process of manufacturing the DRAM of the first embodimentof the invention, respectively;

FIGS. 10A and 10B are fragmentary cross sections of a DRAM of a secondembodiment of the invention;

FIGS. 11A and 11B-12A and 12B are fragmentary cross sections showing 8thand 9th steps in a process of manufacturing the DRAM of the secondembodiment of the invention, respectively;

FIGS. 13A and 13B are fragmentary cross sections of a DRAM of a thirdembodiment of the invention;

FIGS. 14A and 14B-18A and 18B are fragmentary cross sections showing 2ndto 6th steps in a process of manufacturing the DRAM of the thirdembodiment of the invention, respectively;

FIGS. 19A and 19B are fragmentary cross sections of a DRAM of a fourthembodiment of the invention;

FIGS. 20A and 20B-22A and 22B are fragmentary cross sections showing 6thto 8th steps in a process of manufacturing the DRAM of the fourthembodiment of the invention, respectively;

FIGS. 23A and 23B are fragmentary cross sections of a DRAM of a fifthembodiment of the invention;

FIGS. 24A and 24B-27A and 27B are fragmentary cross sections showing 4thto 7th steps in a process of manufacturing the DRAM of the fifthembodiment of the invention, respectively;

FIG. 28 is a block diagram showing a general structure of a DRAM;

FIGS. 29A and 29B are fragmentary cross sections showing an example of aconventional DRAM;

FIGS. 30A and 30B-36A and 36B are fragmentary cross sections showing 1stto 7th steps in a process of manufacturing the conventional DRAM,respectively;

FIG. 37 shows a first problem of the conventional DRAM, and is afragmentary cross section showing a peripheral circuitry of the DRAM ata 5th step in a process of manufacturing the conventional DRAM; and

FIG. 38 shows a third problem of the conventional DRAM, and is afragmentary cross section showing a 7th step in the process ofmanufacturing the conventional DRAM.

DESCRIPTION OF THE PREFERRED EMBODIMENT

Embodiments of the invention will be described below with reference toFIGS. 1A and 1B to 27A and 27B.

First Embodiment

A first embodiment of the invention will now be described below withreference to FIGS. 1A and 1B to 9A and 9B. FIGS. 1A and 1B arefragmentary cross sections of a DRAM of the first embodiment of theinvention. FIGS. 2A and 2B-9A and 9B are fragmentary cross sectionsshowing 1st to 8th steps in a process of manufacturing the DRAM of thefirst embodiment of the invention, respectively.

A structure of the DRAM of the first embodiment of the invention will bedescribed below with reference to FIGS. 1A and 1B. Referring to FIG. 1A,a structure of a memory cell array (memory cell portion) of the DRAM ofthe invention is substantially the same as that of the memory cell arrayof the DRAM in the prior art. A field oxide film 2 is formed at anelement isolating region on a main surface of a semiconductor substrate1 of a p-type.

Transfer transistors 4a and 4b are formed at element forming regions onthe main surface of semiconductor substrate 1. Transfer gate transistor4a includes n-type impurity regions 3a and 3b forming source/drainregions, and a gate electrode (word line) 7a formed on a channel regionbetween impurity regions 3a and 3b with a gate insulating film 6atherebetween.

Transfer gate transistor 4b includes n-type impurity regions 3b and 3cforming source/drain regions, and a gate electrode 7b formed on achannel region between impurity regions 3b and 3c with a gate insulatingfilm 6b therebetween. Gate electrodes 7c and 7d of another transfer gatetransistor are formed on field oxide film 2.

Gate electrodes (word lines) 7a, 7b, 7c and 7d are covered with oxidefilms 9. A buried bit line 10 electrically connected to impurity region3b is formed on the predetermined impurity region 3b. Buried bit line 10is covered with an insulating layer 12. Insulating layer 12 and oxidefilms 9 are covered with a first interlayer insulating film 14 which ismade of a BPSG film and formed on the main surface of semiconductorsubstrate 1.

First interlayer insulating film 14 is provided at predeterminedpositions with first contact holes 15 extending up to surfaces ofimpurity regions 3a, 3c and 3d. First plug electrodes 16, made ofpolysilicon containing impurity introduced thereinto or tungsten (W),are formed in contact holes 15. Barrier layers 29 are formed on the topsurfaces of first plug electrodes 16. Barrier layers 29 may be made ofmaterial such as TiN, Ta, Ti/TiN/Ti or Ti. Barrier layers 29 preventdiffusion between the material of capacitor lower electrode 17 and thematerial of first plug electrode 16.

Capacitor lower electrodes 17 are formed on barrier layers 29. Capacitorlower electrodes 17 may be made of noble metal of a high melting pointsuch as platinum (Pt) or palladium (Pd), and preferably has a filmthickness from about 500 Å to about 2000 Å.

Capacitor lower electrodes 17 are covered with a capacitor dielectricfilm 18. Capacitor dielectric film 18 may be made of material having ahigh dielectric constant such as SrTiO₃ (STO) or PZT, and preferably hasa film thickness from about 500 Å to about 1000 Å.

Capacitor dielectric film 18 is covered with a capacitor upper electrode19. Capacitor upper electrode 19 may be made of noble metal of a highmelting point such as platinum (Pt), and preferably has a film thicknessfrom about 500 Å to about 2000 Å.

Capacitor lower electrodes 17, capacitor dielectric film 18 andcapacitor upper electrode 19 form a capacitor 24.

Capacitor upper electrode 19 is covered with a second interlayerinsulating film 20 made of, e.g., a BPSG film. Second interlayerinsulating film 20 has a film thickness of about 5000 Å to about 8000 Å.

First aluminum interconnection layers 21 are formed on second interlayerinsulating film 20 with a space between each other. First aluminuminterconnection layers 21 are covered with a protective film 22. Asecond aluminum interconnection layer 23 is formed on protective film22.

Then, a structure of a peripheral circuitry (peripheral circuit portion)of the DRAM of the embodiment will be described below. Referring to FIG.1B, the peripheral circuitry is also provided with field oxide films 2at the element isolating regions on the main surface of semiconductorsubstrate 1. AMOS transistor 5 and an impurity region 3e are formed atelement forming regions on the main surface of semiconductor substrate1.

MOS transistor 5 includes impurity regions 3f and 3g formingsource/drain regions, and a gate electrode 8 formed on a channel regionbetween impurity regions 3f and 3g with a gate insulating film 6ctherebetween. Polysilicon pads 11a and 11b are formed on impurityregions 3f and 3g and are electrically connected thereto, respectively.Polysilicon pad 11a is covered with an insulating layer 13.

Polysilicon pads 11a and 11b as well as impurity region 3e are coveredwith first interlayer insulating film 14a, which may be made of a BPSGfilm or the like.

First interlayer insulating film 14a is provided at its predeterminedpositions with second contact holes 15a having a depth from about 300 Åto about 1 μm. Thus, the second contact holes 15a are shallower thansecond contact holes 215a in the prior art. Thereby, the aspect ratio ofsecond contact holes 15a can be smaller than that of second contactholes 215a in the prior art already described.

Second plug electrodes 16a, made of polysilicon containing impurityintroduced thereinto or tungsten (W), are formed in second contact hole15a. Second plug electrodes 16a are preferably made of the same materialas that of first plug electrodes 16 already described.

Pad layers 17a are formed on second plug electrodes 16a. The pad layers17a are preferably made of the same material as capacitor lowerelectrodes 17. Thereby, pad layers 17a can be formed at the same step asthe capacitor lower electrodes 17. This allows formation of pad layers17a in the peripheral circuitry without adding a new step.

In the above structure, a distance between pad layer 17a and theconductive layer on semiconductor substrate 1 is shorter than a distancebetween first aluminum interconnection layer 221a and the conductivelayer on semiconductor substrate 201 in the prior art. As alreadydescribed in connection with the prior art, however, insulation betweenthem can be ensured owing to provision of first interlayer insulatingfilm 14a having the above film thickness between pad layer 17a and theconductive layer on semiconductor substrate 1.

Pad layers 17a extend over the top surfaces of second plug electrodes16a and first interlayer insulating film 14a as shown in FIG. 1. Padlayer 17a is preferably formed to have relatively large top and bottomsurfaces. Thereby, pad layers 17a can be easily connected to second plugelectrodes 16a. Thus, pad layers 17a can be formed easily. This alsoincreases a degree of freedom relating to positions of third contactholes 15b, which will be formed on the pad layers 17a at a later step.Therefore, third contact holes 15b can be formed easily.

Owing to a high degree of freedom relating to positions of third contactholes 15b, third contact holes 15b can be formed at positions shiftedfrom the positions of second contact holes 15a. Thereby, it is possibleto ensure a relatively large area for forming first aluminuminterconnection layers 21a even if the degree of integration increases.As a result, first aluminum interconnection layers 21a can be formedeasily even if the degree of integration increases.

A second interlayer insulating film 20a is formed over pad layer 17a.Second interlayer insulating film 20a preferably has a film thicknessfrom about 5000 Å to about 8000 Å, and may be made of material such asBPSG.

Second interlayer insulating film 20a is provided with third contactholes 15b located above pad layers 17a. Third contact holes 15b has adepth from about 5000 Å to about 8000 Å, which is smaller than that ofsecond contact hole 215a in the prior art. Thereby, the aspect ration ofthird contact holes 15b can be smaller than that of second contact hole215a in the prior art.

Bases of third contact holes 15b are formed of pad layer 17a. Ifplatinum is selected as the material of pad layers 17a, good resistanceagainst over-etching can be obtained when forming third contact holes15b. Owing to the above matters, third contact holes 15b can be formedvery easily.

First aluminum interconnection layers 21a are formed in third contactholes 15b. If platinum is selected as the material of pad layers 17a,the surfaces of pad layers 17a are hardly oxidized, because the platinumis stable metal. Therefore, good contact can be made between firstaluminum interconnection layers 21a and pad layers 17a.

A protective film 22a is formed to cover first aluminum interconnectionlayers 21a. A second aluminum interconnection layer 23a is formed overprotective film 22a.

Referring to FIGS. 2A and 2B to 9A and 9B, a method of manufacturing theDRAM of the first embodiment of the invention shown in FIG. 1 will bedescribed below.

Referring to FIGS. 2A and 2B, the same process as the prior art isperformed to form transfer gate transistors 4a and 4b, buried bit line10, gate electrodes 7c and 7d, and field oxide film 2 in the memory cellarray. Also, MOS transistor 5, polysilicon pads 11a and 11b, and fieldoxide film 2 are formed in the peripheral circuitry. The CVD method orthe like is carried out to form first interlayer insulating films 14 and14 made of, e.g., BPSG films on the whole main surface of semiconductorsubstrate 1. First interlayer insulating films 14 and 14a thus formedpreferably have a film thickness from about 3000 Å to about 1 μm.

Referring to FIGS. 3A and 3B, first contact holes 15 reaching thesurfaces of impurity regions 3a, 3c and 3d are formed at predeterminedpositions in the memory cell array. Simultaneously, second contact holes15a which reach the surfaces of impurity region 3e and polysilicon pads11a and 11b, respectively, are formed at predetermined positions infirst interlayer insulating film 14a of the peripheral circuitry.

Second contact holes 15a in the peripheral circuitry have a depth D3from about 3000 Å to about 1 μm, and also have an open width W1 fromabout 0.6 μm to about 0,8 μm. Therefore, the aspect ratio of secondcontact holes 15a is in a range from about 0.4 to about 1.7, and thus issmaller than the disadvantageously large aspect ration from about 2 toabout 3 of the contact holes 215a formed at the peripheral circuitry inthe prior art. This facilitates formation of second contact holes 15a,compared with second contact holes 215a in the prior art.

Referring to FIGS. 4A and 4B, first and second plug electrodes 16 and16a, e.g., of polysilicon are formed in first and second contact holes15 and 15a in a manner described below, respectively.

First, the CVD method or the like is used to form a polysilicon layer,which fills first and second contact holes 15 and 15a, on the mainsurface of semiconductor substrate. The polysilicon layer thus formedpreferably contains impurity introduced thereinto. Etchback is effectedon the polysilicon layer to form first and second plug electrodes 16 and16a made of polysilicon in first and second contact holes 15 and 15a,respectively.

However, if a CMOS (Complementary Metal Oxide Semiconductor) device isformed in the peripheral circuitry, formation of first and second plugelectrodes 16 and 16a in the above manner may cause a following problemdue to the fact that the CMOS has a pMOS and an nMOS.

The conductivity type of impurity regions 3a, 3b, 3c and 3d formed inthe memory cell array is n-type in this embodiment. Therefore, impurityof n-type is introduced into the polysilicon layer forming first andsecond plug electrodes 16 and 16a. Therefore, second plug electrodes 16acontaining impurity of n-type is formed also on the impurity region ofpMOS. However such a technique increases the resistance of thoseportions having underlying p-type regions.

In order to overcome the above problem, the undoped polysilicon may bedeposited for forming first and second plug electrodes 16 and 16a.Etchback is effected on the undoped polysilicon layer to form plugelectrodes 16 and 16a in first and second contact holes 15 and 15a.Thereafter ion-implantation is carried out to implant n-type impuritiesinto those plugs overlying n-type regions and p-type impurities intothose plugs overlying p-type regions.

Thereby, first and second plug electrodes 16 and 16a are formed. In thismanner, it is possible to form first and second plug electrodes 16 and16a of the conductivity type corresponding to the conductivity type ofimpurity regions formed at the main surface of semiconductor substrate1.

Referring to FIGS. 5A and 5B, a sputtering method or the like is used todeposit a barrier layer on first and second plug electrodes 16 and 16aand first interlayer insulating films 14 and 14a. A platinum layerhaving a predetermined film thickness is deposited on the barrier layer,e.g., by a sputtering method.

The platinum layer and barrier layer are patterned into predeterminedconfigurations. Thereby, barrier layers 29 and capacitor lowerelectrodes 17 are formed in the memory cell array, and simultaneously,barrier layers 29a and pad layers 17a are formed in the peripheralcircuitry.

Pad layer 17a thus formed in the peripheral circuitry preferably has aplan width W2 from about 1 μm to about 2 μm. Pad layers 17a may have anyappropriate shape.

Referring to FIGS. 6A and 6B, capacitor dielectric film 18 is formed tocover capacitor lower electrodes 17 in the memory cell array, e.g., by asputtering method. Capacitor dielectric film 18 is made of highdielectric material such as SrTiO₃.

Capacitor upper electrode 19 made of, e.g., platinum is formed to covercapacitor dielectric film 18, e.g., by a sputtering method. Thereby, thecapacitors 24 including capacitor upper electrode 19, capacitordielectric film 18 and capacitor lower electrodes 17 are formed in thememory cell array 24.

Referring to FIGS. 7A and 7B, second interlayer insulating films 20 and20a made of, e.g., BPSG are formed to cover capacitor upper electrode 19and pad layers 17a by a CVD method or the like, respectively. Secondinterlayer insulating films 20 and 20a preferably have a film thicknessfrom about 5000 Å to about 8000 Å.

Referring to FIGS. 8A and 8B, third contact holes 15b are formed in thesecond interlayer insulating film 20a. Third contact holes 15b arelocated above pad layers 17a. Therefore, the degree of freedom relatingto the positions of third contact holes 15b can be increased, becausepad layers 17a each have a relatively large plan width W2 as alreadydescribed.

Since the film thickness of second interlayer insulating film 20a is ina range from about 5000 Å to about 8000 Å, third contact hole 15b has adepth D4 smaller than the depth D2 of second contact hole 215a in theprior art. Therefore, the aspect ratio of third contact hole 15b issmaller than the aspect ratio of second contact hole 215a in the priorart. Therefore, third contact holes 15b can be formed easily.

Referring to FIGS. 9A and 9B, first aluminum interconnection layers 21are formed on second interlayer insulating film 20 in the memory cellarray with a predetermined space between each other. At the same time,first aluminum interconnection layers 21a are formed in third contactholes 15a of the peripheral circuitry. In connection with this, padlayers 17a are made of platinum, and thus are resistive to oxidation.Therefore, good contact can be obtained between first aluminuminterconnection layers 21a and pad layers 17a.

Thereafter, steps similar to those in the prior art are carried out toform protective films 22 and 22a as well as second aluminuminterconnection layers 23 and 23a. Thereby, the DRAM of the firstembodiment shown in FIGS. 1A and 1B is completed.

Second Embodiment

Referring to FIGS. 10A and 10B to 12A and 12B, a second embodiment ofthe invention will be described below. FIGS. 10A and 10B are fragmentarycross sections showing a DRAM of the second embodiment of the invention.FIGS. 11A and 11B-12A and 12B are cross sections showing 8th and 9thsteps in the process of manufacturing the DRAM of the second embodimentof the invention, respectively.

Referring first to FIGS. 10A and 10B, a structure of the DRAM of thesecond embodiment of the invention will be described be described below.In the embodiment shown in FIG. 10, the peripheral circuitry is providedwith third plugs 25 which are made of tungsten (W) or the like and areformed in third contact holes 15b. The rest of the structure issubstantially the same as the DRAM of the first embodiment. Similarly tothe first embodiment, therefore, second and third contact holes 15a and15b as well as first aluminum interconnection layers 21a can be formedmore easily than the prior art.

Owing to provision of third plug electrodes 25, reliability of thecontacts between first aluminum interconnection layers 21a and padlayers 17a can be improved because of the following reason.

First aluminum interconnection layers 21a are generally formed by thesputtering method. Therefore, they may not closely cover irregular orstepped surfaces. Meanwhile, depth D4 (shown in FIG. 8B) of contact hole15b is smaller than depth D2 (shown in FIG. 37) of second contact hole215a in the peripheral circuitry of the prior art as described above,but has a certain magnitude.

Therefore, if first aluminum interconnection layers 21a were formeddirectly in third contact holes 15b, as in the first embodiment, firstaluminum interconnection layers 21a might break in third contact holes15b because the step coverage of aluminum interconnection layers 21a ispoor.

In contrast to the above, this second embodiment is provided with thirdcontact holes 15b filled with third plug electrodes 25, so that theproblem of breakage of first aluminum interconnection layers 21adescribed above does not substantially generate.

Referring to FIGS. 11A and 11B-12A and 12B, a process of manufacturingthe DRAM of the second embodiment according to the invention will bedescribed below. Referring first to FIGS. 11A and 11B, a process fromthe initial step to the step of forming third contact holes 15 iscarried out similarly to that of the first embodiment. Then, a CVDmethod or the like is used to deposit a conductive layer of tungsten (W)or the like filling third contact holes 15b.

Etchback is effected on conductive layer 25a to form third plugelectrodes 25 in third contact holes 15b as shown in FIGS. 12A and 12B.Thereafter, the same steps as those of the first embodiment are carriedout to form sequentially first aluminum interconnection layers 21a and21, protective films 22 and 22a and second aluminum interconnectionlayers 23 and 23a. Thereby, the DRAM of the second embodiment shown inFIGS. 10A and 10B is completed.

This embodiment uses a process of forming plug electrodes 25 in spite ofthe fact that the process is expensive, and thus the manufacturing costis larger than that of the first embodiment. However, the secondembodiment can further improve the reliability of the contacts betweenpad layers 17a and first aluminum interconnection layers 21a.

Third Embodiment

Then, a third embodiment of the invention will be described below withreference to FIGS. 13A and 13B to 18A and 18B. FIGS. 18A and 18B arefragmentary cross sections showing a DRAM of the third embodiment of theinvention. FIGS. 14A and 14B to 18A and 18B are fragmentary crosssections showing 2nd to 6th steps in a process of manufacturing the DRAMof the third embodiment of the invention.

Referring first to FIGS. 13A and 13B, the structure of the DRAM of thethird embodiment of the invention will be described below. As shown inFIGS. 13A and 13B, this embodiment is provided with a barrier layer 28between an inner surface of each first contact hole 15 and first plugelectrode 16. In this embodiment, barrier layer 28 includes a Ti layer26 and a TiN layer 27 formed on Ti layer 26. Barrier layer 28 may beformed of any other material preventing mutual diffusion between thematerial of plug electrode 16 and the material of semiconductorsubstrate 1.

Likewise, the peripheral circuitry is provided with barrier layers 28aformed between inner surfaces of second contact holes 15a and secondplug electrodes 16a. Each barrier layer 28a includes a Ti layer 26a anda TiN layer 27a formed on Ti layer 26a. Ti layers 26 and 26a preferablyhave a film thickness from about 50 Å to about 100 Å. TiN layers 27 and27a preferably have a film thickness of about 500 Å. The rest of thestructure is substantially the same as that of the first embodiment.Therefore, similarly to the first embodiment, second and third contactholes 15a and 15b as well as first aluminum interconnection layers 21acan be formed more easily than the prior art.

Provision of barrier layers 28 and 28a can achieve advantages, whichwill be described below in connection with two cases, i.e., the casewhere first and second plug electrodes 16 and 16a are made ofpolysilicon and the case where they are made of tungsten (W).

If polysilicon is selected as the material of first and second plugelectrodes 16 and 16a, provision of barrier layers 28 and 28a enableseasy manufacturing even in the case where a CMOS device is formed in theperipheral circuitry.

More specifically, all of second plug electrodes 16a can be set to havethe same conductivity type. Therefore, it is not necessary to carry oution implantation for changing the conductivity type of second plugelectrode 16a, which is required in the first embodiment. Consequently,second plug electrodes can be formed easily.

Owing to provision of barrier layers 28 and 28a, it is possible to makeohmic contact between the impurity regions formed on the main surface ofsemiconductor substrate 1 and first and second plug electrodes 16 and16a. Therefore, the contact resistance can be reduced.

If tungsten (W) is selected as the material of first and second plugelectrodes 16 and 16a, provision of barrier layers 28 and 28a canprevent reaction of semiconductor substrate 1 and the tungsten (W). Alsoowing to provision of barrier layers 28 and 28a, adhesion betweensemiconductor substrate 1 and first and second plug electrodes 16 and16a can be improved compared with the case where barrier layers 28 and28a are not provided.

A process of manufacturing the DRAM of the third embodiment of theinvention will be described below with reference to FIGS. 14A and 14B to18A and 18B. Referring to FIG. 14A and 14B, a process from the initialstep to the step of forming first interlayer insulating films 14 and 14ais carried out similarly to that of the first embodiment. However incontrast to the first embodiment, polysilicon pads 11a and 11b are notformed on impurity regions 3f and 3g in the peripheral circuitryaccording to this embodiment.

Polysilicon pads 11a and 11b can provide such a merit that a maximumallowable magnitude of dislocation of a mask can be relatively largewhen forming second contact holes 15a. However, provision of polysiliconpads 11a and 11b unpreferably complicates the manufacturing steps.Therefore, it is preferable not to form polysilicon pads 11a and 11b ifpossible.

In view of the above matters, this embodiment is designed not to providepolysilicon pads 11a and 11b. Therefore, a maximum allowable magnitudeof dislocation of the mask can be relatively small when forming secondcontact holes 15a, but the manufacturing cost can be reduced.

Anisotropic etching is effected on first interlayer insulating films 14and 14a to form first and second contact holes 15 and 15a reaching thesurfaces of impurity regions 3a, 3c, 3d, 3e, 3f and 3g. Referring toFIGS. 15A and 15B, a sputtering method or the like is used to form Tilayer 26 and TiN layer 27 on first interlayer insulating films 14 and14a including inner surfaces of first and second contact holes 15 and15a.

A CVD method or the like is used to deposit on TiN layer 27 a conductivelayer 16b, for example, made of tungsten (W) or polysilicon containingimpurity introduced thereinto. In this step, conductive layer 16b isformed to fill first and second contact holes 15 and 15a.

Then, etchback is effected on conductive layer 16b. Thereby, as shown inFIGS. 16A and 16B, first and second plug electrodes 16 and 16a areformed in first and second contact holes 15 and 15a.

Then, etching is effected on TiN layers 27 and 27a and TiN layers 26 and26a. Thereby, Ti layers 26 and 26a and TiN layers 27 and 27a areremained only in first and second contact holes 15 and 15a as shown inFIGS. 17A and 17B.

Referring to FIGS. 18A and 18B, barrier layers 29 and capacitor lowerelectrodes 17 are formed on first plug electrodes 16 by the same methodas the first embodiment. At the same time, barrier layers 29a and padlayers 17a are formed over the top surfaces of second plug electrodes16a and first interlayer insulating films 14a in the peripheralcircuitry.

Thereafter, the same steps as those in the first embodiment are carriedout to form capacitor dielectric film 18, capacitor upper electrode 19,second interlayer insulating films 20 and 20a, first aluminuminterconnection layers 21 and 21a, protective films 22 and 22a, andsecond aluminum interconnection layers 23 and 23a. Thereby, the DRAM ofthe third embodiment shown in FIGS. 13A and 13B is completed.

According to the manufacturing method of this embodiment, barrier layers28 and 28a are added to the structure of the first embodiment. This maycomplicate the manufacturing steps to a certain extent. However,reliability, performance and others of the DRAM can be improved further.

Fourth Embodiment

Referring to FIGS. 19A and 19B to 22A and 22B, a DRAM of a fourthembodiment of the invention will be described below. FIG. 19A and 19Bare fragmentary cross sections showing the DRAM of the fourth embodimentof the invention. FIGS. 20A and 20B to 22A and 22B are fragmentary crosssections showing 6th to 8th steps in a process of manufacturing the DRAMof the fourth embodiment of the invention.

Referring first to FIGS. 19A and 19B, a structure of the DRAM of thefourth embodiment of the invention will be described below. Thisembodiment is a modification of the third embodiment described before,and differs from the third embodiment in that third plug electrodes 25are formed in third contact holes 15b. Other structure is the same asthat of the third embodiment. Owing to this structure, reliability ofthe contacts between first aluminum interconnection layers 21a and padlayers 17a can be improved in comparison with the third embodiment, asthe second embodiment can improve the reliability in comparison with thefirst embodiment.

Referring to FIGS. 20A and 20B to 22A and 22B, a method of manufacturingthe DRAM of the fourth embodiment of the invention will be describedbelow. Referring to FIGS. 20A and 20B, a process from the initial stepto the step of forming second interlayer insulating films 20 and 20a iscarried out similarly to that of the third embodiment.

Referring to FIGS. 21A and 21B, third contact holes 15b are formed atsecond interlayer insulating film 20a in the peripheral circuitry by thesame method as the second embodiment. Third plug electrodes 25 areformed in third contact holes 15b by the same method as the secondembodiment.

Referring to FIGS. 22A and 22B, first aluminum interconnection layers 21are formed on second interlayer insulating film 22 in the memory cellarray with a predetermined space between each other. At the same time,first aluminum interconnection layers 21a are formed on third plugelectrodes 25 in the peripheral circuitry.

Thereafter, the same steps as those of the first embodiment are carriedout to form protective films 22 and 22a as well as second aluminuminterconnection layers 23 and 23a. Thereby, the DRAM of the fourthembodiment shown in FIGS. 19A and 19B is completed.

Also in this embodiment, second and third contact holes 15a and 15b canbe formed more easily than the prior art, similarly to the embodimentsalready described. Although formation of plug electrodes 25 increasesthe manufacturing cost to a certain extent, it improves the reliability.

Fifth Embodiment

Referring to FIGS. 23A and 23B to 27A and 27B, a DRAM of a fifthembodiment of the invention will be described below. FIGS. 23A and 23Bare fragmentary cross sections showing the DRAM of the fifth embodimentof the invention. FIGS. 24A and 24B to 27A and 27B are fragmentary crosssections showing 4th to 7th steps in a process of manufacturing the DRAMof the fifth embodiment of the invention.

This embodiment will be described in view of the fact that the inventionis applicable to a DRAM which does not use films made of high dielectricmaterial as the capacitor dielectric films.

Referring first to FIGS. 23A and 23B, a structure of the DRAM of thefifth embodiment of the invention will be described below. As shown inFIGS. 23A and 23B, this embodiment includes capacitor lower electrodes17b each having a structure which integrally includes capacitor lowerelectrode 17 and plug electrode 16 in the third embodiment shown in FIG.13A.

Pad layers 17c formed in the peripheral circuitry each have a structurewhich integrally includes pad layer 17a and second plug electrode 16ashown in FIG. 13B. Pad layers 17c and capacitor lower electrodes 17b maybe made of polysilicon.

In this embodiment, capacitor dielectric film 18 is made of an ONO filmor the like. Capacitor upper electrodes 19a are made of polysilicon.Other structure is the same as that of the third embodiment shown inFIGS. 13A and 13B.

Owing to the above structures of capacitor lower electrodes 17b and padlayers 17c, the manufacturing steps can be simpler than those of thethird embodiment. In the third embodiment, capacitor lower electrodes 17and pad layers 17a are formed at the step different from that of formingfirst and second plug electrodes 16 and 16a. This embodiment, however,can form them at the same step. Therefore, the manufacturing steps canbe simpler than those of the third embodiment.

Similarly to the embodiments already described, the embodiment can formsecond and third contact holes 15a and 15 as well as first aluminuminterconnection layers 21a more easily than the prior art.

Referring to FIGS. 24A and 24B to 27A and 27B, a method of manufacturingthe DRAM of the fifth embodiment of the invention will be describedbelow. Referring to FIGS. 24A and 24B, a process from the initial stepto the step of forming TiN layers 27 and 27a is carried out similarly tothat of the third embodiment. Then, a CVD method or the like is used toform polysilicon layers 17b and 17c on TiN layers 27 and 27a,respectively. Resist patterns 30 and 30b which are patterned intopredetermined configurations are formed on polysilicon layers 17b and17c.

Referring to FIGS. 25A and 25B, polysilicon layers 17b and 17c, TiNlayers 27 and 27a, and Ti layers 26 and 26a are sequentially etchedusing resist pattern 30 and 30a as a mask. Thereby, barrier layers 28and 28a, capacitor lower electrodes 17b and pad layers 17c are formed.

Referring to FIGS. 26A and 26B, capacitor dielectric film 18a made of anONO film is formed to cover capacitor lower electrodes 17b. A CVD methodor the like is used to form capacitor upper electrode 19a made ofpolysilicon or the like and covering capacitor dielectric film 18a.

Referring to FIGS. 27A and 27B, a CVD method or the like is used to formsecond interlayer insulating films 20 and 20a made of BPSG films tocover capacitor upper electrode 19a and pad layers 17c. Third contactholes 15b are formed at portions of second interlayer insulating film20a located above pad layers 17c in the peripheral circuitry.

Thereafter, the same steps as those of the third embodiment are carriedout to form first aluminum interconnection layers 21 and 21a, protectivefilms 22 and 22a and second aluminum interconnection layers 23 and 23a.Thereby, the DRAM of the fifth embodiment shown in FIGS. 23A and 23B iscompleted. In the embodiments described before, the interlayerinsulating films (14 and 20) formed in the memory cell array are made ofthe same material as the interlayer insulating films (14a and 20a)formed in the peripheral circuitry. However, different materials may beused.

According to the semiconductor memory device of the invention, asdescribed hereinbefore, it is not necessary to form openings (contactholes) of a large aspect ratio in the peripheral circuitry, as is donein the prior art. Therefore, the openings can be formed easily in theperipheral circuitry. The pad layer is formed in the peripheralcircuitry for making contact between the main surface of thesemiconductor substrate and the interconnection layer. The pad layer maybe extended over the top surface of the first interlayer insulatingfilm, which increases the degree of freedom relating to the position ofthe third opening. Thereby, the third opening and interconnection layercan be formed easily even if the degree of integration furtherincreases.

The pad layer and capacitor lower electrode may be made of the samematerial, in which case the pad layer and capacitor lower electrode canbe formed at the same step, simplifying the manufacturing process.Thereby, the manufacturing cost can be reduced. The first plug electrodeand capacitor lower electrode may be integral with each other, and thesecond plug electrode and pad layer may be integral with each other, inwhich case the manufacturing process can be simplified further. Thereby,the manufacturing cost can be further reduced.

Metal of a high melting point such as platinum may be selected as thematerial of the pad layer, in which case good contact can be madebetween the interconnection layer and pad layer, and the third contacthole 15b can be formed easily.

According to the method of manufacturing the semiconductor memory deviceof one aspect of the invention, the pad layer formed at the same step asthe capacitor lower electrode is remained. Thereby, the second and thirdopenings formed in the peripheral circuitry can be shallower than theopenings in the peripheral circuitry of the prior art. Thereby, thesecond and third openings can be formed easily. The pad layer can beformed of have a top surface or a bottom surface of a relatively largearea. Thereby, it is possible to increase the degree of freedom of theposition at which the third opening is formed. Therefore, the thirdopening can be formed easily.

Further, it is possible to eliminate a conventional step of forming aplug for electrically connecting the interconnection layer to the mainsurface of the semiconductor substrate in the peripheral circuitry.Thereby, the manufacturing steps can be simpler than those of the priorart, and thus the manufacturing cost can be reduced.

According to the method of manufacturing the semiconductor memory deviceof another aspect of the invention, the capacitor lower electrode isintegral with the first plug electrode, and the pad layer is integralwith the second plug electrode. Thereby, the capacitor lower electrodeand first plug electrode can be formed at the same step, and the padlayer and second plug electrode can be formed at the same step.Therefore, the manufacturing steps can be further simplified.Consequently, the manufacturing cost can be further reduced.

Although the present invention has been described and illustrated indetail, it is clearly understood that the same is by way of illustrationand example only and is not to be taken by way of limitation, the spiritand scope of the present invention being limited only by the terms ofthe appended claims.

What is claimed is:
 1. A semiconductor memory device including a memorycell portion and a peripheral circuit portion on a main surface of asemiconductor substrate, said memory cell portion including memory cellsfor storing information and said peripheral circuit portion includingperipheral circuits for controlling an operation of said memory cells,said semiconductor memory device, comprising;a first interlayerinsulating film which is provided with a first opening at apredetermined position in said memory cell portion of said semiconductorsubstrate and a second opening at a predetermined position in saidperipheral circuit portion of said semiconductor substrate; first andsecond plug electrodes formed in said first and second openings,respectively; a capacitor lower electrode formed on and electricallyconnected to said first plug electrode; a capacitor dielectric filmcovering said capacitor lower electrode; a capacitor upper electrodecovering said capacitor dielectric film; a pad layer formed on a topsurface of said second plug electrode and a top surface of said firstinterlayer insulating film and electrically connected to said secondplug electrode; a second interlayer insulating film formed on said padlayer and having a third opening located above said pad layer; and aninterconnection layer formed at least in said third opening andelectrically connected to said pad layer.
 2. A semiconductor memorydevice according to claim 1, wherein said pad layer and said capacitorlower electrode are made of the same material.
 3. A semiconductor memorydevice according to claim 1, wherein said capacitor lower electrode andsaid first plug electrode are integral with each other, and said padlayer and said second plug electrode are integral with each other.
 4. Asemiconductor memory device according to claim 1, wherein said pad layerand said capacitor lower electrode are made of noble metal having a highmelting point.
 5. A semiconductor memory device according to claim 4,wherein said capacitor lower electrode and said pad layer are made of atleast one material selected from the group consisting of Pt and Pd.
 6. Asemiconductor memory device according to claim 1, wherein said capacitordielectric film is made of material having a high dielectric constant.7. A semiconductor memory device according to claim 1, wherein said padlayer further comprises a first layer formed on a top surface of saidsecond plug electrode and a second layer formed on top of said firstlayer, wherein said first layer is formed of a material which isnonreactive with a material of said second plug electrode.
 8. Asemiconductor memory device according to claim 1, wherein said capacitorlower electrode further comprises a first layer formed on top surface ofsaid first plug electrode and a second layer formed on top of said firstlayer, wherein said first layer is formed of a material which isnon-reactive with a material of said first plug electrode and saidsecond layer forms a substrate for said dielectric material.
 9. Asemiconductor memory device according to claim 1, wherein each of saidfirst and second plug electrodes comprise polysilicon selectivelyion-implanted with an impurity type corresponding to that portion of thesemiconductor substrate underlying a corresponding one of said first andsecond plug electrodes.
 10. A semiconductor memory device according toclaim 1, wherein said third opening is formed on said pad layerpositioned on said top surface of said first interlayer insulating film.